1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor, and more particularly, to a method for manufacturing a capacitor capable of realizing a high integration by utilizing an aluminum oxide as a capacitor insulating layer having a high dielectric constant, improving characteristics of a semiconductor device by using a low temperature vapor deposition and a low temperature annealing, improving leakage current characteristics by utilizing titanium as an upper electrode of the capacitor and reducing manufacturing costs by simplifying the capacitor manufacturing process.
2. Description of the Related Art
Generally, a capacitor plays a role in storing electrical charges and supplying charges required to operate a semiconductor device, it tends to decrease the size of the unit cell with high integration of the semiconductor device, whereas it tends to slightly increase the capacitance required to operate the semiconductor device.
Thus, as the high integration of the semiconductor device is realized, scaling down the capacitor is required, however, there is a limit in storing the electrical charges, whereby the capacitor shows a problem in the high integration in comparison to its size.
As a result, each manufacturer has diversely changed the structure of capacitor to store electrical charges, there are various methods to increase the charges to be stored in the capacitor, e.g., a method utilizing a material with a high dielectric constant as a capacitor dielectric for increasing the charges of the capacitor, a method reducing the thickness of a dielectric material for increasing the charges of the capacitor, a method increasing the area of the capacitor for increasing the charge of the capacitor or the like, however, recently the method which increases the area of the capacitor has been widely employed to increase the charge of the capacitor.
Accordingly, if the capacitor is approximately classified in view of the structure of a charge storage electrode, there are two type of structures: one is a stacked structure of the electrode to obtain a wide area of the capacitor by stacking a number of layers on a narrow area for storing the electrical charges and the other is a trench structure which forms a trench in a semiconductor substrate to a predetermined depth to form the capacitor in the trench for storing the electrical charges speed.
FIGS. 1a to 1j show a method for forming a capacitor by utilizing a trench structure selected among conventional capacitor manufacturing methods. The conventional capacitor manufacturing method is described hereinafter.
As shown in FIG. 1a, a field region and an active region are separately formed on a semiconductor substrate 2 by performing various processes, and then, a transistor 4 is formed on the active region.
And, an interlayer insulating layer 6 is formed on the resultant structure to thereby obtain a planarization and contact holes are formed to connect the active region of the semiconductor substrate 2 through a mask etching process.
Thereafter, as shown in FIGS. 1b and 1c, a doped poly layer 10 is formed on the resultant structure which serves as a lower electrode of the capacitor and a phospho-silicate glass (PSG) insulating layer 12 is formed thereon.
Subsequently, a photoresist layer 14 is formed on the resultant structure, a portion to define a capacitor is remained by patterning and the capacitor is formed by a dry etching.
And then, as shown in FIG. 1d, a doped poly layer 10 is formed on the resultant structure.
In the next step, as shown in FIG. 1e, the doped poly layer 10 at the remaining portion except a side portion of the capacitor is removed by dry etching a front of the resultant structure.
As shown in FIG. 1f, a low electrode of the capacitor to form a spatial part of a cylindrical shape is formed by removing the PSG insulating layer 12 remaining at a center portion of the capacitor in the resultant structure through a wet etching.
Thereafter, as shown in FIG. 1g, a native oxide is grown at the lower electrode of the capacitor, a nitride layer is deposited on the native oxide and a capacitor insulating layer 18 is formed by oxidizing the nitride layer.
After the doped poly layer 20 is formed on the resultant structure, the region of the capacitor is blocked by a photoresist layer 22.
In an ensuing step, as shown in FIG. 1h, after a second interlayer insulating layer 24 is formed on the resultant structure, contact holes 26 are formed in the second interlayer insulating layer 24 by using a photolithography and an etching processes.
In the following step, as shown in FIG. 1i, a plug metal, especially made of tungsten, is filled in the contact holes 26 so as to bury the contact holes 26, thereby forming a plurality of metal plugs 28.
As shown in FIG. 1j, metal lines 30 are formed on the metal plugs 28 to connect the metal plugs 28 thereto and to use as an interconnection.
In accordance with the conventional capacitor manufacturing method described above, it requires a number of processes to generate a capacitor, which, in turn, cause a number of fails to be created by the defects and particles generated during the processes; and therefore, a repair circuit is required to compensate for the defects and particles to thereby causing problems in increasing the area of chip due to the repair circuit.
Also, it is difficult to implement dry etching and bury the plug metal, since the contact holes formed for connecting the metal lines for use in an interconnection have depths of approximately 20000 Å.
Further, since the position at the center is etched to expose both an upper electrode of a capacitor and the active region of the silicon substrate during formation of contact holes at the second interlayer insulating layer, the contact characteristics of the capacitor deteriorate when in contact with a safe active region and it is difficult to control the lower transistor characteristics due to the high temperature applied during oxidation of the nitride layer.